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CMOS Latched 4-/8-Channel Analog Multiplexers ADG528A/ADG529A
FEATURES 44 V Supply Maximum Rating VSS to VDD Analog Signal Range Single-/Dual-Supply Specifications Wide Supply Ranges (10.8 V to 16.5 V) Microprocessor Compatible (100 ns WR Pulse) Extended Plastic Temperature Range (-40C to +85C) Low Leakage (20 pA typ) Low Power Dissipation (28 mW max) Available in 18-Lead DIP/SOIC and 20-Lead PLCC Packages Superior Alternative to: DG528 DG529 FUNCTIONAL BLOCK DIAGRAMS
GENERAL DESCRIPTION
PRODUCT HIGHLIGHTS
The ADG528A and ADG529A are CMOS monolithic analog multiplexers with eight channels and four dual channels, respectively. On-chip latches facilitate microprocessor interfacing. The ADG528A switches one of eight inputs to a common output, depending on the state of three binary addresses and an enable input. The ADG529A switches one of four differential inputs to a common differential output, depending on the state of two binary addresses and an enable input. Both devices have TTL and 5 V CMOS logic-compatible digital inputs. The ADG528A and ADG529A are designed on an enhanced LC2MOS process, which gives an increased signal capability of VSS to VDD and enables operation over a wide range of supply voltages. The devices can comfortably operate anywhere in the 10.8 V to 16.5 V single- or dual-supply range. These multiplexers also feature high switching and low RON.
1. Single-/dual-supply specifications with a wide tolerance. The devices are specified in the 10.8 V to 16.5 V range for both single- and dual-supplies. 2. Easily Interfaced The ADG528A and ADG529A can be easily interfaced with microprocessors. The WR signal latches the state of the address control lines and the enable line. The RS signal clears both the address and enable data in the latches resulting in no output (all switches off). RS can be tied to the microprocessor reset pin. 3. Extended Signal Range The enhanced LC2MOS processing results in a high breakdown and an increased analog signal range of VSS to VDD. 4. Break-Before-Make Switching Switches are guaranteed break-before-make so that input signals are protected against momentary shorting. 5. Low Leakage Leakage currents in the range of 20 pA make these multiplexers suitable for high precision circuits.
REV. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 www.analog.com Fax: 781/326-8703 (c) 2004 Analog Devices, Inc. All rights reserved.
ADG528A/ADG529A-SPECIFICATIONS
DUAL SUPPLY
(VDD = +10.8 V to +16.5 V, VSS = -10.8 V to -16.5 V, unless otherwise noted.)
ADG528A ADG529A K Version -40C to +25C +85C VSS VDD 280 450 300 RON Drift RON Match IS (OFF), Off Input Leakage ID (OFF), Off Input Leakage ADG528A ADG529A ID (ON), On Channel Leakage ADG528A ADG529A IDIFF, Differential Off Output Leakage (ADG529A only) 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 100 50 100 50 25 2.4 0.8 1 8 200 300 50 25 200 300 200 300 100 VSS VDD 600 400 ADG528A ADG528A ADG529A ADG529A B Version T Version -40C to -55C to +25C +85C +25C +125C VSS VDD 280 450 300 0.6 5 0.02 1 0.04 1 1 0.04 1 1 50 100 50 100 50 25 2.4 0.8 1 8 200 300 50 25 200 300 200 300 100 VSS VDD 600 400 VSS VDD 280 450 300 0.6 5 0.02 1 0.04 1 1 0.04 1 1 VSS VDD 600 400
Parameter ANALOG SWITCH Analog Signal Range RON
Units V min V max typ max max max %/C typ % typ nA typ nA max nA typ nA max nA max nA typ nA max nA max nA max V min V max A max pF max ns typ ns max ns typ ns min ns typ ns max ns typ ns max ns min ns min ns min ns min dB typ dB min pF typ pF typ pF typ pC typ
Comments
-10 V VS +10 V, IDS = 1 mA; Test Circuit 1 VDD = 15 V ( 10%), VSS = -15 V (10%) VDD = 15 V ( 5%), VSS = -15 V ( 5%) -10 V VS +10 V, IDS = 1 mA -10 V VS +10 V, IDS = 1 mA V1 = 10 V, V2 = V1 = 10 V, V2 = 10 V; Test Circuit 2 10 V; Test Circuit 3
50 100 50 100 50 25 2.4 0.8 1
V1 = 10 V, V2 =
10 V; Test Circuit 4
V1 = 10 V, V2 =
10 V; Test Circuit 5
DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance 8
VIN = 0 to VDD
DYNAMIC CHARACTERISTICS 1 tTRANSITION 200 300 400 tOPEN 50 25 10 tON (EN, WR) 200 300 400 tOFF (EN, RS) 200 300 400 tW Write Pulse Width 100 120 tS Address, Enable Setup Time 100 tH, Address, Enable Hold Time 10 tRS Reset Pulse Width 100 OFF Isolation 68 50 5 CS (OFF) CD (OFF) ADG528A 22 ADG529A 11 QINJ, Charge Injection 4
V1 = 10 V, V2 = Test Circuit 7
10 V; Test Circuit 6
400 10 400 400 120 100 10 100
400 10 400 400 130 100 10 100
Test Circuits 8 and 9 Test Circuits 8 and 10 See Figure 1 See Figure 1 See Figure 1 See Figure 2 VEN = 0.8 V, RL = 1 k, CL = 15 pF, VS = 7 V rms, f = 100 kHz VEN = 0.8 V VEN = 0.8 V RS = 0 , VS = 0 V; Test Circuit 11
68 50 5 22 11 4
68 50 5 22 11 4
-2-
REV. B
ADG528A/ADG529A
ADG528A ADG529A K Version -40C to +25C +85C 0.6 1.5 ISS Power Dissipation 20 0.2 10 2.8
NOTE 1 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
Parameter POWER SUPPLY IDD
ADG528A ADG528A ADG529A ADG529A B Version T Version -40C to -55C to +25C +85C +25C +125C 0.6 1.5 20 0.2 10 2.8 10 2.8 20 0.2 0.6 1.5
Units
Comments
mA typ VIN = VINL or VINH mA max A typ VIN = VINL or VINH mA max mW typ mW max
SINGLE SUPPLY
(VDD = +10.8 V to +16.5 V, VSS = GND = 0 V, unless otherwise noted.)
ADG528A ADG529A K Version -40C to +25C +85C GND GND VDD VDD 500 ADG528A ADG528A ADG529A ADG529A B Version T Version -40C to -55C to +25C +85C +25C +125C GND GND VDD VDD 500 1000 700 0.6 5 0.02 1 0.04 1 1 0.04 1 1 1000 GND GND VDD VDD 500 700 0.6 0.02 1 0.04 1 1 0.04 1 1 1000 5 50 100 50 100 50 25 50 100 50 100 50 25
Parameter ANALOG SWITCH Analog Signal Range RON
Units V min V max typ
Comments
RON Drift RON Match IS (OFF), Off Input Leakage ID (OFF), Off Input Leakage ADG528A ADG529A ID (ON), On Channel Leakage ADG528A ADG529A IDIFF, Differential Off Output Leakage (ADG529A only)
700 0.6 5 0.02 1 0.04 1 1 0.04 1 1
max %/C typ GND VS +10 V, IDS = 0.5 mA % typ GND VS +10 V, IDS = 0.5 mA nA typ nA max nA typ nA max nA max nA typ nA max nA max nA max
GND VS +10 V, IDS = 0.5 mA; Test Circuit 1
50 100 50 100 50 25
V1 = +10 V/GND, V2 = GND/+10 V; Test Circuit 2 V1 = +10 V/GND, V2 = GND/+10 V; Test Circuit 3 V1 = +10 V/GND, V2 = GND/+10 V; Test Circuit 4
V1 = +10 V/GND, V2 = GND/+10 V; Test Circuit 5
DIGITAL CONTROL VINH, Input High Voltage VINL, Input Low Voltage IINL or IINH CIN Digital Input Capacitance 8 DYNAMIC CHARACTERISTICS tTRANSITION 300 tOPEN tON (EN, WR) tOFF (EN, RS) tW Write Pulse Width 450 50 25 250 450 250 450 100
1
2.4 0.8 1 8 300 600 10 600 600 120 450 50 25 250 450 250 450 100
2.4 0.8 1 8 300 600 10 600 600 120 450 50 25 250 450 250 450 100
2.4 0.8 1
V min V max A max pF max ns typ
VIN = 0 to VDD
V1 = +10 V/GND, V2 = GND/+10 V; Test Circuit 6 Test Circuit 7 Test Circuits 8 and 9 Test Circuits 8 and 10 See Figure 1
600 10 600 600 130
ns max ns typ ns min ns typ ns max ns typ ns max ns min
REV. B
-3-
ADG528A/ADG529A
ADG528A ADG529A K Version -40C to +25C +85C
1
Parameter
ADG528A ADG528A ADG529A ADG529A B Version T Version -40C to -55C to +25C +85C +25C +125C
Units
Comments
DYNAMIC CHARACTERISTICS tS Address, Enable Setup Time tH Address, Enable Hold Time tRS Reset Pulse Width OFF Isolation 68 50 5 CS (OFF) CD (OFF) ADG528A 22 ADG529A 11 QINJ, Charge Injection 4 POWER SUPPLY IDD 0.6 Power Dissipation 11
(Cont'd) 100 10 100 68 50 5 22 11 4 0.6 1.5 10 25 25 1.5 10 25 100 10 100 68 50 5 22 11 4 0.6 1.5 100 10 100 ns min ns min ns min dB typ dB min pF typ pF typ pF typ pC typ See Figure 1 See Figure 1 See Figure 2 VEN = 0.8 V, RL = 1 k, CL = 15 pF, VS = 3.5 V rms, f = 100 kHz VEN = 0.8 V VEN = 0.8 V RS = 0 , VS = 0 V; Test Circuit 11
mA typ VIN = VINL or VINH mA max mW typ mW max
NOTE 1 Sample tested at +25C to ensure compliance. Specifications subject to change without notice.
-4-
REV. B
ADG528A/ADG529A
PIN CONFIGURATIONS DIP/SOIC PLCC ABSOLUTE MAXIMUM RATINGS 1
(TA = +25C, unless otherwise noted) VDD to VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 V VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 V VSS to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -25 V Analog Inputs2 Voltage at S, D . . . . . . . . . VSS - 2 V to VDD + 2 V or 20 mA, whichever Occurs First Continuous Current, S or D . . . . . . . . . . . . . . . . . . . 20 mA Pulsed Current, S or D 1 ms duration, 10% Duty Cycle . . . . . . . . . . . . . . . 40 mA Digital Inputs1 Voltage at A, EN, WR, RS . . . . . . VSS - 4 V to VDD + 4 V or 20 mA, whichever Occurs First Power Dissipation (Any Package) Up to +75C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 470 mW Derates above +75C . . . . . . . . . . . . . . . . . . . . . . . 6 mW/C Operating Temperature Commercial (K Version) . . . . . . . . . . . . . . . -40C to +85C Industrial (B Version) . . . . . . . . . . . . . . . . . -40C to +85C Extended (T Version) . . . . . . . . . . . . . . . . -55C to +125C Storage Temperature Range . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . +300C
NOTES 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 Overvoltage at A, EN, WR, RS, S or D will be clamped by diodes. Current should be limited to the maximum rating above.
ORDERING GUIDE
Model ADG528AKN ADG528AKP ADG528AKP-REEL ADG528ABQ ADG528ATQ ADG528ABCHIPS ADG528ATCHIPS ADG529AKN ADG529AKP ADG529AKRW ADG529AKRW-REEL ADG529AKRW-REEL7 ADG529ABQ ADG529ATQ ADG529ABCHIPS ADG529ATCHIPS
Temperature Range -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C
Package Description PDIP PLCC PLCC CERDIP CERDIP DIE DIE PDIP PLCC SOIC SOIC SOIC CERDIP CERDIP DIE DIE
Package Option1 N-18 P-20A P-20A Q-18 Q-18
-40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -40C to +85C -55C to +125C
N-18 P-20A RW-18 RW-18 RW-18 Q-18 Q-18
NOTES 1 N = Plastic DIP; P = Plastic Leaded Chip Carrier (PLCC); Q = Cerdip; RW = SOIC.
CAUTION ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the human body and test equipment and can discharge without detection. Although the ADG528A/ADG529A features proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. B
-5-
ADG528A/ADG529A
TRUTH TABLES TIMING DIAGRAMS
A2 A1 A0 EN WR RS ON SWITCH PAIR X X X 0 0 0 0 1 1 1 1 X X X 0 0 1 1 0 0 1 1 X X X 0 1 0 1 0 1 0 1 X X 0 1 1 1 1 1 1 1 1 X 0 0 0 0 0 0 0 0 0 1 0 1 1 1 1 1 1 1 1 1 Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 5 6 7 8 ADG528A
Figure 1.
X = Don't Care
A1 A0 EN WR RS ON SWITCH PAIR X X X 0 0 1 1 X X X 0 1 0 1 X X 0 1 1 1 1 X 0 0 0 0 0 1 0 1 1 1 1 1 Retains Previous Switch Condition NONE (Address and Enable Latches Cleared) NONE 1 2 3 4 ADG529A
Figure 2.
Figure 1 shows the timing sequence for latching the switch address and enable inputs. The latches are level sensitive; therefore, while WR is held low, the latches are transparent and the switches respond to the address and enable inputs. This input data is latched on the rising edge of WR. Figure 2 shows the Reset Pulse Width, tRS, and Reset Turn-off Time, tOFF (RS). Note: All digital input signals rise and fall times measured from 10% to 90% of 3 V. tR = tF = 20 ns.
X = Don't Care
-6-
REV. B
Typical Performance Characteristics-ADG528A/ADG529A
The multiplexers are guaranteed functional with reduced single or dual supplies down to 4.5 V.
TPC 1. RON as a Function of VD(VS): Dual Supply Voltage, TA = +25C
TPC 4. Trigger Levels vs. Power Supply Voltage, Dual or Single Supply, TA = +25C
TPC 2. Leakage Current as a Function of Temperature (Note: Leakage Currents Reduce as the Supply Voltages Reduce)
TPC 5. tTRANSITION vs. Supply Voltage: Dual and Single Supplies, TA = +25C (Note: For VDD and |VSS| < 10 V; V1 = VDD/VSS, V2 = VSS/VDD. See Test Circuit 6)
TPC 3. RON as a Function of VD(VS): Single Supply Voltage, TA = +25C
TPC 6. IDD vs. Supply Voltage: Dual or Single Supply, TA = +25C
REV. B
-7-
ADG528A/ADG529A Test Circuits
Test Circuit 1. RON
Test Circuit 4. ID (ON)
Test Circuit 2. IS (OFF)
Test Circuit 5. IDIFF
Test Circuit 3. ID (OFF)
Test Circuit 6. Switching Time of Multiplexer, tTRANSITION
Test Circuit 7. Break-Before-Make Delay, tOPEN
-8-
REV. B
ADG528A/ADG529A
Test Circuit 8. Enable Delay, tON (EN), tOFF (EN)
Test Circuit 9. Write Turn-On Time, tON (WR)
Test Circuit 10. Reset Turn-Off Time, tOFF (RS)
Test Circuit 11. Charge Injection
REV. B
-9-
ADG528A/ADG529A
TERMINOLOGY
RON RON Match RON Drift IS (OFF) ID (OFF) ID (ON) VS (VD) CS (OFF) CD (OFF) CIN tON (EN)
Ohmic resistance between terminals D and S Difference between the RON of any two channels Change in RON versus temperature Source terminal leakage current when the switch is off. Drain terminal leakage current when the switch is off. Leakage current that flows from the closed switch into the body. Analog voltage on terminal S or D Channel input capacitance for "OFF" condition Channel output capacitance for "OFF" condition Digital input capacitance Delay time between the 50% and 90% points of the digital input and switch "ON" condition.
tOFF (EN) tTRANSITION
tOPEN
VINL VINH IINL (IINH) VDD VSS IDD ISS
Delay time between the 50% and 10% points of the digital input and switch "OFF" condition Delay time between the 50% and 90% points of the digital inputs and switch "ON" condition when switching from one address state to another. "OFF" time measured between 50% points of both switches when switching from one address state to another Maximum input voltage for Logic "0" Minimum input voltage for Logic "1" Input current of the digital input Most positive voltage supply Most negative voltage supply Positive supply current Negative supply current
OUTLINE DIMENSIONS
18-Lead Plastic Dual In-Line Package [PDIP] (N-18)
Dimensions shown in inches and (millimeters)
0.885 (22.48) 0.845 (21.46)
18 1 10 9
0.295 (7.49) 0.275 (6.99)
0.180 (4.57) MAX
0.325 (8.26) 0.300 (7.62) 0.015 (0.38) MIN
0.180 (4.57) MAX
0.150 (3.81) 0.110 (2.79)
SEATING 0.100 0.060 (1.52) PLANE 0.022 (0.558) (2.54) 0.045 (1.14) 0.014 (0.356) BSC
0.015 (0.381) 0.008 (0.203)
COMPLIANT TO JEDEC STANDARDS MO-095AD CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
20-Lead Plastic Leaded Chip Carrier [PLCC] (P-20A)
Dimensions shown in inches and (millimeters)
0.180 (4.57) 0.165 (4.19) 0.056 (1.42) 0.042 (1.07)
19 18
0.048 (1.21) 0.042 (1.07)
3
0.20 (0.51) MIN 0.021 (0.53) 0.013 (0.33)
0.020 (0.50) R
0.048 (1.21) 0.042 (1.07)
4
TOP VIEW
(PINS DOWN) 8 14 9 13
0.050 (1.27) BSC
0.330 (8.38) 0.032 (0.81) 0.290 (7.37) 0.026 (0.66) 0.040 (1.01) R 0.025 (0.64) 0.120 (3.04) 0.090 (2.29)
BOTTOM VIEW
(PINS UP)
0.020 (0.50) R
0.356 (9.04) 0.350 (8.89) SQ 0.395 (10.02) SQ 0.385 (9.78)
COMPLIANT TO JEDEC STANDARDS MO-047AA CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
-10-
REV. B
ADG528A/ADG529A
OUTLINE DIMENSIONS 18-Lead Ceramic Dual In-Line Package [CERDIP] (Q-18)
Dimensions shown in inches and (millimeters)
0.005 (0.13) MIN PIN 1
1 9
0.098 (2.49) MAX
18 10
0.310 (7.87) 0.220 (5.59)
0.200 (5.08) MAX 0.200 (5.08) 0.125 (3.18) 0.023 (0.58) 0.014 (0.36)
0.960 (24.38) MAX
0.060 (1.52) 0.015 (0.38) 0.150 (3.81) MIN 15 0
0.320 (8.13) 0.290 (7.37) 0.015 (0.38) 0.008 (0.20)
0.100 (2.54) BSC
0.070 (1.78) SEATING PLANE 0.030 (0.76)
CONTROLLING DIMENSIONS ARE IN INCHES; MILLIMETER DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF INCH EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
18-Lead Standard Small Outline Package [SOIC] Wide Body (RW-18)
Dimensions shown in millimeters and (inches)
11.75 (0.4626) 11.35 (0.4469)
18
10
7.60 (0.2992) 7.40 (0.2913)
1 9
10.65 (0.4193) 10.00 (0.3937)
0.30 (0.0118) 0.10 (0.0039) 1.27 (0.0500) BSC
2.65 (0.1043) 2.35 (0.0925)
0.75 (0.0295) 0.25 (0.0098)
45
COPLANARITY 0.10
8 0.51 (0.0201) SEATING 0.33 (0.0130) 0 0.31 (0.0122) PLANE 0.20 (0.0079)
1.27 (0.0500) 0.40 (0.0157)
COMPLIANT TO JEDEC STANDARDS MS-013AB CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS (IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
REV. B
-11-
ADG528A/ADG529A Revision History
Location 10/04--Data Sheet Changed from Rev. A to Rev. B Page
Deleted 20-Lead LCC package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 SOIC added to DIP PIN CONFIGURATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
C03337-0-10/04(B)
Changes to FEATURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
-12-
REV. B
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